System and method for cleaning contact elements and support hardware using functionalized surface microfeatures

ABSTRACT

A cleaning material, device, and method for predictably cleaning the contact elements and support hardware of a tester interface, such as a probe card and a test socket, in which the cleaning pad has a predetermined configuration appropriate for the particular pin contact elements and a substrate having a defined functionalized surface topology and geometry which can be introduced into the testing apparatus during the normal testing operations. The cleaning material has a predetermined topography with a plurality of functional 3-dimensional (3D) microstructures that provide performance characteristics which are not possible with a non-functionalized and flat surface.

PRIORITY CLAIMS

This application is a divisional of and claims priority under 35 USC 120 and 121 to U.S. patent application Ser. No. 16/684,453 filed Nov. 14, 2019, the entirety of which is incorporated herein by reference.

FIELD

The disclosure relates generally to a material, device, and method for predictably and consistently cleaning tester interface contact elements and support hardware such as probe-cards and test sockets.

BACKGROUND

Individual semiconductor (integrated circuit) devices are typically produced by creating a plurality of devices on a semiconductor wafer using well known semiconductor processing techniques that can include photolithography, deposition, and sputtering. Generally, these processes are intended to create fully-functional integrated circuit devices (ICs) at the wafer level. Eventually, the individual IC devices are singulated, or diced, into the separate and individual dies from the semiconductor wafer. The singulated IC devices are assembled for final completion in packages or incorporation into electronic apparatus using well known assembly techniques that can include die attach to a lead-frame, wire bonding or solder ball attach, and encapsulation usually by various molding techniques to provide a body to the package with external electrical connectivity.

In practice, however, physical defects in the wafer itself and/or defects in the processing of the wafer can inevitably lead to some of the dies on the wafer being either fully functional, some of the dies being non-functional, and some of the dies have lower performance or in need of repair. It is generally desirable to identify which of the dies on a wafer are fully functional preferably prior to singulation from the wafer and assembly into consumer devices. Non-functional, lower performing, and repairable devices due to certain physical defects in the wafer, defects in the IC circuit layers, and/or defects related to the semiconductor processing techniques can be identified prior to singulation by a process called wafer-level test (often referred to in the arts as “wafer sort”). Sorting, or binning, IC devices at the wafer level according to the product's capabilities where the product performance is determined by electrical testing can save the manufacturer considerable costs later in the manufacturing process as well as provide increased revenue from the sales of the highest performing devices.

Once the device has been singulated, certain process steps during handling and assembly can inevitably lead to dicing defects, handling defects, assembly and packaging related defects that can only be identified electrically to bin devices as fully-functional, non-functional, or potentially “repair-able”. In practice, assembled and packaged semiconductor devices are subject to a series of electrical testing processes prior to their final completion or incorporation into electronic apparatus. The process at package level or final test prior to shipment includes, but is not limited to, testing of singulated devices either bare die, packaged IC (temporary or permanent), or variants in between.

Commonly, electrical testing of the IC devices at either the wafer level or package level is accomplished by means of automatic test equipment (ATE) configured mechanically and electrically for stimulating the semiconductor devices, exercising the device according to adaptive testing techniques and functional routines, and examining the output for assessing proper functionality.

At wafer level test, conventional interface hardware is a “probe card” to which pluralities of probe elements that match the layout of the device under test (DUT) input/output (I/O) pads, power, GND and process monitoring pins are connected. More specifically, in the typical wafer testing process, the probe card is mounted to the prober, and probe contact elements (simply referred to as “probes”) are brought into contact with bonding pads, solder balls, bumps, pillars, or pillar bumps formed on the dies of the wafer. By exerting controlled displacement of the probe tips against the bonding pads, solder balls, bumps, pillars, or pillar bumps an electrical connection is achieved allowing the power, ground and test signals to be transmitted. Repeated scrub, deformation, and penetration of the probe tips against the bonding pads, solder balls, bumps, pillars, or pillar bumps produces debris and contaminants that adhere and accumulate onto the probe contact surface.

At the package level test, a tester load board provides an interface between automated test equipment (ATE), or manual test equipment, and the DUT. The tester load board conventionally includes one or more contactor assemblies, sometimes referred to as “test socket(s)” into which DUT(s) is (are) inserted. During the testing process, a DUT is inserted or placed into the socket by the handler and held into position for the duration of testing. After insertion into the socket, the DUT, via the pin elements, is electrically connected to the

ATE through the tester load board, its subassemblies, and other interfacing apparatus. Contact pin elements associated with the ATE are placed in physical and electrical contact with the metallized contact surfaces of the DUT. These surfaces may include test pads, lead wire, pin connectors, bond pads, solder balls, and/or other conductive media. The functionality, static and dynamic performance tests of DUTs is evaluated through various electrical inputs and measured responses on outputs. With repeated testing, the contact element tip can become contaminated with materials such as aluminum, copper, lead, tin, gold, bi-products, organic films or oxides resulting from the wafer and semiconductor device manufacturing and testing processes.

One of the major challenges encountered with both types of IC testing (wafer level and package level) is ensuring optimal electrical contact between the contact pins associated with the contactor element, and the contact surfaces of the DUT. In each test procedure, with repeated contact the pin contact elements onto bonding pads, solder balls, bumps, pillars, or pillar bumps, debris and other residuals will accumulate and contaminate the contact area of the pin elements. This debris may originate from the testing and handling process itself or may include manufacturing residue from the device fabrication and/or assembly process(es) or from other sources.

In addition to the presence of contaminants, repeatedly forcing electrical current through the small intermetallic “a-spots” of the contact pins can degrade the conductivity characteristics of contact surfaces, thus affecting the inter-metallic quality for proper electrical testing. As the contaminants accumulate, coupled with degradation of contact surfaces, the contact resistance (CRES) rises and reduces the reliability of the tests. Increasing and unstable CRES can impact yield and/or test time as yield recovery testing increases. Such erroneous readings can lead to the false rejection of otherwise good DUTs resulting in, often dramatic, yield loss. Yield recovery may be possible through multi-pass testing; however, retesting devices multiple times to verify a device or to attain yield recovery causes the overall production costs to increase, reduce throughput, affect assembly, and create a possibility for reductions in long-term reliability.

High performance demands for wafer level and package level test contactor technologies have furthered the development of uniquely shaped and customized contact elements with predetermined and engineered mechanical and electrical performance properties. Many of the new advanced contact technologies have unique contact element geometries and mechanical behavior to facilitate consistent, repeatable, and stable electrical contact. Some of the technologies are constructed using lithographic assembly techniques, some are built using MEMS based processes; while others are fabricated with high accuracy micro-machining techniques. Improved electrical characteristics of the contactors are also attained using various materials with improved electrical performance and resistance to oxidation. The contact elements are engineered to facilitate consistent oxide penetration while reducing the applied bearing force onto the bonding pads, solder balls, bumps, pillars, or pillar bumps. However, it is still necessary to make physical contact with the bonding pads, solder balls, bumps, pillars, or pillar bumps; thereby, generating debris and contamination that could affect the results from the electrical performance testing procedures.

Typically, the generated debris needs to be periodically removed from the contact elements to prevent a build-up that causes increased contact resistance, continuity failures and false test indications, which in turn result in artificially lower yields and subsequent increased product costs and reduced throughput.

In response to the problem of particles adhering to the contact element and supporting hardware, a few techniques have been developed. For example, one technique uses cleaning materials composed of a silicone rubber which provides a matrix for abrasive particles. In addition, a cleaning wafer, or a cleaning medium mounted onto an abrasive ceramic cleaning block which is rubbed against the probe needles may be used or a rubber matrix with abrasive particles and a brush cleaner made of glass fibers also may be used. In one technique, the probe needles may be sprayed or dipped in a cleaning solution. In another technique, open cell foam based cleaning device with a random surface morphology of voids and variable heights may be used.

In one conventional contact element cleaning process, some combination of brushing, blowing, and rinsing the contact pins and/or contactor bodies are employed. This process requires stopping the testing operation, manual intervention to perform the cleaning, and possibly removing the test interface (probe card, socket, etc.) from the test environment. This method provides inconsistent debris removal and may not provide sufficient cleaning action within the geometric features of shaped contact elements. After cleaning, the test interface must be reinstalled, and the test environment reestablished so that testing may resume. In some cases, the contact elements are removed, cleaned, and replaced resulting in elevated costs due to unscheduled equipment downtime.

In another conventional method, a cleaning pad with an abrasive surface coating or abrasively coated polyurethane foam layer is used to remove foreign materials adhering to the contact elements. Adherent foreign materials are abraded off the contact elements and supporting hardware by repeatedly scrubbing the contact elements against (and possibly into) the cleaning pad. The process of cleaning using an abrasive pad burnishes the contact element, but it does not necessarily remove debris. In fact, the burnishing causes abrasive wear to the contact elements thereby changing the shape of the contact geometry, changing the contact performance, and shortening the useful life of the contactor.

Maximum cleaning efficiency is attained when the removal of the debris from the contact element and supporting hardware is performed consistently and predictably during the cleaning process without affecting the performance of the contact elements. The process of cleaning using an abrasive pad constructed from open celled foam does not provide consistent cleaning. In fact, the burnishing action by the randomly oriented and uncontrolled foam structures causes non-uniform abrasive wear as well as preferential abrasive wear to the contact elements thereby unpredictably changing the shape of the contact geometry and mechanical performance of the contact element and support hardware; thereby, unpredictably shortening the useful life of the contactor.

In the industry, it has been seen that the tester interface hardware consisting of a plurality of contact elements, as many as 150,000 test probe elements, and the support hardware can cost more than $1M per ATE test cell. Premature wear-out and damage due to improper or non-optimal cleaning practices can equate to millions of US dollars per annum per ATE test cell. Therefore, with tens of thousands of ATE test cells operating worldwide, the impact to the repair, maintenance, and replacement costs can be very substantial.

Another attempt to improve upon the conventional probe cleaning process includes using a tacky abrasively filled or unfilled polymeric cleaning material to remove the foreign materials. More specifically, the polymer pad is brought into physical contact with the contact elements. Adherent debris is loosened by the tacky polymer and sticks to the polymer surface; thereby removed from the contact elements and other test hardware. The polymer materials are designed to maintain the overall shape of the contact elements; however, interaction with the polymer layer may not provide sufficient cleaning action within the geometric features of shaped contact elements.

When cleaning with abrasively filled or abrasively coated materials films that have a continuous, uniform surface or a surface with randomly oriented and randomly spaced surface features, preferential abrasion is manifested through “edge pin” effects (for example, peripheral contact elements of a test probe array are abrasively worn at different rates than the contact element within the array); or through “neighbor pin spacing” effects (for example, closely spaced contact elements are worn at different rates than widely spaced contact elements); or through “neighbor pin orientation” effects (for example, spatial proximity of contact elements can cause preferential and asymmetric wear of contact elements). Non-uniform abrasive wear of contact elements and support hardware will affect the performance consistency during the IC semiconductor device testing and could result in unexpected yield loss, equipment downtime, and repair costs.

Typical contact element cleaning processes at wafer level and package level can be expensive for the end-user since the contactors may be uncontrollably worn away at different rates by the abrasive-based contact cleaning processes. When using abrasive particles of the rate of wear-out or dimensional reduction for critical contact element geometries can be dramatically affected by relatively small changes (approximately 2 to 3%) to the compliance of the abrasive material layers, surface features, and that of the under-layers. With thousands of IC device testing units (probers and handlers) operating worldwide, the impact to the industry from maintaining clean contact elements without premature wear out during testing can be very substantial.

None of these methods adequately clean these testing machines nor the contact elements of these testing machines that have critical contact element geometries. Accordingly, there is a need for improved methods and apparatuses for cleaning and maintaining the contact elements.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A illustrates a conventional example of a device under test, or DUT, at wafer level or at package level with probe pads; electrical contact elements, and an ATE interface (probe card or test socket);

FIG. 1B is a schematic of an example of a device under test, or DUT, at wafer level or at package level solder bumps, pillars, or bumped pillars, electrical contact elements, and an ATE interface (probe card or test socket);

FIG. 2A is a top view of a typical cleaning device with cleaning pad that can be applied to a wafer surface;

FIG. 2B is a sectional view of a typical cleaning device with a cleaning pad applied to a substrate surface;

FIG. 2C is a sectional view of a typical cleaning device with a cleaning pad applied to a substrate that approximates an IC package;

FIG. 3A is a sectional view of a known cleaning medium that has one or more intermediate complaint material layers below a cleaning pad layer of predetermined properties and a protective liner;

FIG. 3B is a sectional view of a known cleaning medium with one or more intermediate rigid material layers below a cleaning pad layer of predetermined properties and a protective liner;

FIG. 4A is an isometric view of a cleaning pad layer with a plurality of evenly spaced and predefined, “positive” micro-pyramids with predetermined properties;

FIG. 4B is an isometric view of a cleaning pad layer with a plurality of evenly spaced and predefined, “positive” micro-columns with predetermined properties;

FIG. 4C is an isometric view of a cleaning pad layer with a plurality of evenly spaced and predefined, “positive” curved pyramidal microfeatures with predetermined properties;

FIG. 5 is a sectional view of a cleaning medium that has one or more intermediate complaint material layers below a cleaning pad layer with a plurality of evenly spaced and predefined, “positive” microfeatures which are above the surface reference plane and a removable protective liner;

FIG. 6A is an isometric view of a cleaning pad layer with a plurality of evenly spaced and predefined, “negative” micro-pyramids with predetermined properties;

FIG. 6B is an isometric view of a cleaning pad layer with a plurality of evenly spaced and predefined, “negative” micro-columns with predetermined properties;

FIG. 6C is an isometric view of a cleaning pad layer with a plurality of evenly spaced and predefined, “negative” inverted curved pyramidal microfeatures with predetermined properties;

FIG. 7 is a sectional view of a cleaning medium that has one or more intermediate complaint material layers below a cleaning pad layer with a plurality of evenly spaced and predefined, “negative” microfeatures and a removable protective liner;

FIG. 8A is a sectional view of a cleaning media layer with predetermined properties such as tack, hardness, abrasiveness, etc., applied to a plurality of evenly spaced and predefined, “positive” micro-pyramids with predetermined properties;

FIG. 8B is a sectional view of a cleaning media layer with predetermined properties such as tack, hardness, abrasiveness, etc., applied to a plurality of evenly spaced and predefined, “positive” micro-columns with predetermined properties;

FIG. 8C is a sectional view of a cleaning media layer with predetermined properties such as tack, hardness, abrasiveness, etc., applied to a plurality of evenly spaced and predefined, “positive” curved pyramidal microfeatures with predetermined properties;

FIG. 8D is a sectional view of a cleaning media layer with predetermined properties such as tack, hardness, abrasiveness, etc., applied to a plurality of evenly spaced and predefined, “positive” [right] micro-pyramids with predetermined properties with one or more intermediate complaint or rigid material layers below a cleaning pad layer of predetermined properties and a protective liner;

FIG. 8E is a sectional view of a cleaning media layer with predetermined properties such as tack, hardness, abrasiveness, etc., applied to a plurality of evenly spaced and predefined, “positive” micro-columns with predetermined properties with one or more intermediate complaint or rigid material layers below a cleaning pad layer of predetermined properties and a protective liner;

FIG. 8F is a sectional view of a cleaning media layer with predetermined properties such as tack, hardness, abrasiveness, etc., applied to a plurality of evenly spaced and predefined, “positive” curved pyramidal microfeatures with predetermined properties with one or more intermediate complaint or rigid material layers below a cleaning pad layer of predetermined properties and a protective liner;

FIG. 9A is a sectional view of a cleaning media layer with predetermined properties such as tack, hardness, abrasiveness, etc., applied to a plurality of evenly spaced and predefined, “negative” micro-pyramids with predetermined properties;

FIG. 9B is a sectional view of a cleaning media layer with predetermined properties such as tack, hardness, abrasiveness, etc., applied to a plurality of evenly spaced and predefined, “negative” micro-columns with predetermined properties;

FIG. 9C is a sectional view of a cleaning media layer with predetermined properties such as tack, hardness, abrasiveness, etc., applied to a plurality of evenly spaced and predefined, “negative or inverted” curved pyramid microfeatures with predetermined properties;

FIG. 9D is a sectional view of a cleaning media layer with predetermined properties such as tack, hardness, abrasiveness, etc., applied to a plurality of evenly spaced and predefined, “negative” micro-pyramids with predetermined properties with one or more intermediate complaint or rigid material layers below a cleaning pad layer of predetermined properties and a protective liner;

FIG. 9E is a sectional view of a cleaning media layer with predetermined properties such as tack, hardness, abrasiveness, etc., applied to a plurality of evenly spaced and predefined, “negative” micro-columns with predetermined properties with one or more intermediate complaint or rigid material layers below a cleaning pad layer of predetermined properties and a protective liner;

FIG. 9F is a sectional view of a cleaning media layer with predetermined properties such as tack, hardness, abrasiveness, etc., applied to a plurality of evenly spaced and predefined, “negative or inverted” curved pyramid microfeatures with predetermined properties with one or more intermediate complaint or rigid material layers below a cleaning pad layer of predetermined properties and a protective liner;

FIG. 10A is an example of a representative package with an array of solder bumps, or solder balls, that are contacted during package test;

FIG. 10B is an example of a cleaning device built for use within a test socket that has a cleaning material layer of predetermined properties such as tack, hardness, abrasiveness, etc., with cleaning material bump, or ball, features that emulate the geometry of the IC packaged device under test and the array of solder ball interconnect;

FIG. 11A is a sectional view of a cleaning media built with a plurality of cleaning balls that can be applied to a predetermined substrate such that the device approximates the geometry of a packaged IC device and can be handled by the test equipment during package level testing;

FIG. 11B is a sectional view of a cleaning media layer with predetermined properties such as tack, hardness, abrasiveness, etc., that has been applied across the plurality ball shaped microfeatures in order to improve the cleaning performance of the ball shaped microfeatures and the cleaning surface during the socket cleaning execution at package level test;

FIG. 12 is a flowchart showing a method for cleaning semiconductor devices using the various embodiments of the disclosed cleaning material.

FIGS. 13A and 13B illustrate probe tip cleaning using a typical cleaning material; and

FIGS. 14A and 14B illustrate the same probe tips as FIGS. 13B being cleaned using the functionalized microfeatures cleaning material.

DETAILED DESCRIPTION OF ONE OR MORE EMBODIMENTS

The disclosure is particularly applicable to a cleaning pad for electrical test probes that have contact elements with predetermined geometries and mechanical performance. The contact elements being cleaned can be any type of test probe, such as cantilever wire needles, vertical probes, cobra probes, MEMS type vertical and MEMS type microcantilever probes, plunger probes, spring probes, sliding contacts, contact bump probes formed on a membrane, etc., and the associated support structures used for tester interface devices utilized for wafer level and package level testing (i.e., probe cards, test sockets, and other similar interface devices). It is in this context that the disclosure will be described; however, it can be appreciated that the cleaning material, device, and method have greater utility, such as cleaning test interfaces utilized by other types of IC semiconductor device evaluation equipment, such as spring pin ring interfaces, ZIFF male/female connectors, etc.

In one embodiment, a cleaning device and method are disclosed that incorporate a cleaning pad construction with a surface functionalization, or surface tunability. Surface functionalization with predetermined microfeatures of custom geometries effectively facilitates adjustable behavior altering the mechanical properties of a cleaning surface in order to achieve specific performance goals such as contact surface cleaning, tip shaping, debris removal and collection, and surface texturing. Materials with structurally functionalized well-regulated structures surfaces contain microscale features that are produced in a controlled manner through imprinting, molding, casting, coating, film deposition, spray deposition or other surface modifications at a microscale level, with the purpose for improving the material cleaning efficiency and mechanical performance. In addition, the equipment and manual labor to repair and replace contactors that have been worn away by an abrasive contact cleaning process adds additional costs to the task performed.

In one embodiment, the cleaning material may be a complaint, semi-rigid, or rigid media that has a surface functionalized with 3-dimensional (3D) microfeatures that provide performance characteristics not possible with flat, non-functionalized surfaces for having specific abrasive and debris removal efficacies to clean electrical contact elements and structures used for tester interfaces devices utilized for wafer level and package level testing (i.e., probe cards, test socket, and other similar interface devices). Surface functionalization, or surface tunability, with adjustable behavior is an effective way for altering the mechanical properties of a cleaning surface to achieve specific performance goals such as contact surface cleaning, tip shaping, debris removal and collection, and surface texturing. Materials with structurally functionalized surfaces contain microscale features that are produced in a controlled manner through imprinting, molding, casting, coating, film deposition, spray deposition or other surface modifications at a microscale level, with the purpose for improving the material cleaning efficiency and mechanical performance.

In one embodiment, a functionalized coating with predetermined properties, such as thickness, hardness, tack, etc., can be applied to the surface of the cleaning pad, across existing structural features, and across microfeatures to provide a new class of cleaning materials that can be tailored and optimized for electrical contact elements and structures applications and perform a well-defined set of functions. A high level of cleaning efficacy can be obtained through functionalizing the cleaning surface in order to emulate the pads, bumps, or pillars of a semiconductor device combined with tacky or abrasive surface coatings, exposed abrasive particles for variable abrasive efficiency, and depending on the type and shape of contact elements being cleaned, the composition and the quantity of debris to be removed, and the affinity of the debris to the contact surface.

In more detail, a functionalized cleaning material may be constructed with the predetermined pads, bumps, or pillars surface features or functional surface coatings on top of one or more support layers, each with predetermined mechanical, material, and dimensional characteristics, such as abrasiveness, density, elasticity, tackiness, planarity, thickness, porosity, etc. The cleaning device may have a sacrificial top protective layer of material that may be applied before, during, or after the fabrication process to protect and isolate the cleaning material surface from contamination during manufacturing process and manual handling operations. The sacrificial layer is removed upon installation into the semiconductor or other testing equipment and is used to ensure that the working surface of the cleaning material is free of any contamination that would compromise the cleaning performance of the contact elements by cleaning material.

The cleaning layer and functionalized 3D-surface features may be made of solid elastomeric materials or porous, open celled or closed foam materials that may include rubbers and both synthetic and natural polymers as well as polyurethanes, acrylics, etc., or other known elastomeric materials. The functionalized surface features may have predetermined abrasiveness, elasticity, density and surface energy parameters that may allow the contact elements to deform and penetrate the elastomeric material to remove the debris from the contact area without damage to the geometry of the contact elements, while retaining the integrity of the elastomeric matrix.

The cleaning material also may have a multi-layered structure in which one or more complaint layers are arranged or stacked to attain a predetermined overall performance so that when the pin or contact elements touch and deform the functionalized features and the pad surface, a defined reciprocal force is imparted by the material into the contact area and 3D structures to increase the efficiency at which the debris and contaminants are removed.

In one embodiment (examples of which are shown in FIGS. 4A-4C and 5), the cleaning material may have a surface layer populated with a plurality of predefined, “positive” geometric microfeatures such as columns, pyramids, or other such structural microfeatures, of a pre-determined aspect ratio (diameter or length and width to height), cross-section (square, circular, triangular, etc.). In another embodiment (examples of which are shown in FIGS. 6A-6C and 7), the cleaning material may have a surface layer populated with a plurality of predefined “negative” or “inverse” geometric microfeatures. The “positive” and “negative” microfeatures may be made of solid elastomeric materials or closed foam materials that may include rubbers and both synthetic and natural polymers as well as polyurethanes, acrylics, polymers, etc., or other known elastomeric materials. The surface layer may have abrasive particle loading or exposed abrasives to improve debris removal and collection efficiency.

In other embodiments, the “positive” and “negative” microfeatures may have abrasive particles applied to the top surface, along the length of the microfeature, within the body of the microfeature, or at the base of the micro-feature. In particular, a typical microfeature (whether a positive microfeature or a negative microfeature) could have varying cross-section widths of 15-μm or less, with a height of 400-μm or less, at a spacing of 250-μm or less and an average abrasive particle size of less than 30 um. Typical abrasives that may be incorporated into and across the material layers and features may include aluminum oxide, silicon carbide, tantalum oxide, and diamond although the abrasive particles may also be other well-known abrasive materials with Mohs Hardness of 7 or greater.

In other embodiments, the microfeatures are built, molded, or formed with a predetermined geometry to attain a predetermined compliance and movement so that when the pin or contact elements touch the pad surface, a reciprocal force is imparted by the material into the contact area, within the contact element tip geometry, and support structures to increase the efficiency at which the debris and contaminates are removed. The functional microfeatures have predetermined dimensions to provide predictable and uniform reciprocal forces onto each test probe within the contact element array and supporting hardware.

In another aspect of the cleaning device, the micro-features may have a particular surface matte or patterned texture or finish such that the prober/tester device is capable of detecting the surface of the cleaning pad. The surface texture and roughness of the cleaning material may also contribute to the cleaning efficiency of the working surface polymer material.

In one aspect of the method, the cleaning medium may be manually placed within the automated test equipment, such as a wafer prober or packaged device handler, in a predetermined location so that pin elements and surfaces will interact with the cleaning medium periodically to remove debris and/or clean the contact surfaces of the pin or contact elements without excessively wearing out the test probe. In another aspect of the method, a method for cleaning the probe elements on a wafer prober or package device handler is provided wherein the method comprises loading the cleaning medium into the wafer prober or package device handler in a form similar to a semiconductor wafer, a singulated IC device, or a packaged IC device being tested and the cleaning medium having a top surface of functionalized microfeatures that have predetermined properties, such as abrasiveness, tack, hardness, that clean the contact elements and support structure. The method further comprises contacting the contact elements with the cleaning medium during the normal testing operation in wafer prober or package device handler so that any debris is removed from the probe elements during the normal operation of the wafer prober or package device handler.

When the prober/tester can detect the surface of the cleaning pad, then the prober is able to be set into an automatic cleaning mode. In the automatic cleaning mode, the prober/tester will automatically determine when to clean the test probe contact elements, locate the cleaning device, clean the probe tips and then return to testing operations. After repeated touchdowns on the devices under test (DUTs), pad materials and other surface contaminants will be accumulated on the test probe contact elements as well as the test probe length. Such loose debris can substantially increase the contact resistance, leading to decreased wafer and package yields. High contact resistance or consecutive failing devices (binouts) can trigger the tester to send a command to the semiconductor device handling machine such that a cleaning operation is executed with an “on demand” functionality. Alternatively, the semiconductor device handling machine can be programmed to execute the cleaning operation at LOT start, LOT end, or after a predetermined number of device touchdowns. As a result, scheduled and efficient cleaning procedure is very critical in controlling contact resistance.

In another embodiment of the cleaning device, the layers of the cleaning medium may be formed from conductive, insulative or resistive materials such that a tester/prober that detects a surface using conductance or capacitive method is able to detect the surface of the cleaning medium.

A typical IC semiconductor testing system (shown schematically in FIGS. 1A and 1B) typically includes some type of tester 10, a test head 11, a tester interface 12 (e.g., probe card or test socket), contact elements 13, and a wafer or device handler 16. The electrical contact elements 13, or test probes, within the tester interface extend from the tester interface to allow direct contact with the DUT 15. DUTs (wafers, singulated devices, or packaged ICs) are moved using automated, semi-automatic, or manual equipment into the appropriate physical position such that probe pads 14 and/or solder balls 16 are in alignment with the contact elements 13 of the tester interface 12. Once in position, the DUT 15 is moved against the contact elements 13 or the contact elements 13 are moved against the DUT 15 for electrical testing. With repeated touchdowns, the contact elements become contaminated. Instead of the removing the test interface for cleaning, the cleaning medium of a predetermined construction will remove contamination during the normal testing operation.

FIGS. 2A, 2B, and 2C illustrate three typical different types of cleaning devices manufactured with a cleaning medium applied to various substrate materials, different size substrates, different shape substrates or without a substrate for some applications. As shown in FIGS. 2A and 2B, cleaning device 20 and 21, respectively, may include a substrate 23 and a cleaning medium, or pad, 24 secured, adhered, or applied to a surface of a wafer or to substrate of known geometry, respectively. The substrate 23 may be polymer, plastic, metal, glass, silicon wafer, ceramic, or any other similar (rigid, semi-rigid or flexible) material Furthermore, a substrate 25 may have a formfactor or structure that approximates the geometry of the packaged IC device, or DUT, 22 whereby the cleaning medium 24 is attached to the surface bearing the contact elements of the test probes and supporting hardware.

FIGS. 3A and 3B illustrate an existing cleaning medium 220 made from a cleaning pad layer 202 of predetermined properties, such as hardness, elastic modulus, tack, etc., and some combination of compliant under-layers 203 (FIG. 3A) or rigid under-layers 206 (FIG. 3B), that contribute to the cleaning of the contact elements that contact the pad. The cleaning medium 220 may also have a removable protective layer 201 that is installed prior to the intended usage for contact element cleaning in order to isolate the surface cleaning pad layer from non-test related contaminants. The cleaning medium 220 can have one or more intermediate layers 203 and 206 attached to and below the cleaning pad layer. The combinations of layers produce material properties unavailable from the individual constituent materials, while the combinations of matrix, abrasive particles, and geometries can maximize cleaning performance. Installation of the cleaning device onto the predetermined substrate material is performed by removal a second release liner layer 205 (made of the same material as the first release liner layer) to expose the adhesive layer 204, followed by application onto the substrate surface by the adhesive layer 204. The adhesive layer 204 may then be placed against a substrate to adhere the cleaning device 220 to the substrate. The substrate may be a variety of different materials as described in the prior art which have different purposes.

Now, a cleaning medium with functional microfeatures is described in more detail with reference to the accompanying drawings and embodiments. As shown, for example in FIG. 5, a cleaning media 221 may have abrasiveness that loosens and shears debris from contact elements. Using pre-determined volumetric and mass densities of abrasive particles; the abrasiveness of the pad can be systematically affected in order to round or sharpen the probe tips. Typical abrasive material and particle weight percentage loading within the cleaning material layer can range for 0% (unloaded) to 500% weight percent. Typical abrasives that may be incorporated into the materials may include aluminum oxide, silicon carbide, and diamond although the abrasive material may also be other well-known abrasive materials. The abrasive may include spatially or preferentially distributed particles of aluminum oxide, silicon carbide, or diamond although the abrasive particles may also be other well-known abrasive materials with Mohs Hardness of 7 or greater. Controlled surface tackiness of the cleaning layer will cause debris on the contact element to preferentially stick to the pad and therefore be removed from the contact element during the cleaning operation. The abrasive particles may be distributed in the body of each microfeature as described below.

In an embodiment of the cleaning medium 221 (shown in FIG. 5), a maximum cleaning efficiency of the cleaning material 221 can be improved using a plurality of “positive” uniformly shaped and regularly spaced, geometric microfeatures in a microfeature layer 250. Examples of different embodiments of the positive microfeatures are shown in

FIGS. 4A-4C that show a plurality of micro-pyramids 401, a plurality of micro-columns 403, or a plurality of curved micro-pyramids 405, of a pre-determined geometry. In FIG. 5, the cleaning media 221 is constructed from a single layer of cleaning pad with “positive” microfeatures 250 onto a combination of intermediate compliant or rigid layers 207 with pre-determined predetermined properties. In other embodiments, the microfeatures may be variably spaced across the cleaning medium 221. The cleaning pad layers 202 and 203 described above and the cleaning pad layers described below the cleaning material reference plane 255 may provide predetermined mechanical, material, and dimensional characteristics to the cleaning material. For example, the cleaning pad layer may provide abrasiveness (described in more detail below), a specific gravity (of a range of 0.75 to 2.27 for example) wherein specific gravity is the ratio of the density to the density of water at a particular temperature, elasticity (of a range of 40-MPa to 600-MPa for example), tackiness (of a range of 20 to 800 grams for example), planarity, and thickness (a range between 25-um and 300-um for example). The selection of the materials and the layers is determined based on the required reciprocal force necessary to facilitate an effective cleaning action. For example, high rigidity materials will have a greater reciprocal that would be required in the removal of tenaciously adherent materials. Highly compliant materials would be selected when cleaning fragile or small diameter contact elements.

As an example of one type of functional “positive” microfeature construction, the microfeatures shown in FIGS. 4A, 4B, 4C can be created using a combination of precision fabrication methods such as casting or molding whereby the cleaning pad is built such that a plateau of each microfeature (a top portion 406 of each microfeature) has a dimension of less than 40um, a height of each microfeature from a base reference plane 408 of less than 500 um, and a plateau-to-plateau spacing (a distance between each microfeature) of less than 250 um. In the example 401 shown in FIG. 4A, each pyramid microfeature 402 has a 25 um square plateau, with a 40 um height, at a plateau-to-plateau spacing of 100 um. For this construction, the 3D features are attained through a precision fabrication process such that the cleaning pad and functionalized microfeatures have a uniform composition. The size and geometry of the “positive” microfeatures may vary according the configuration and material of the contact elements to achieve a pad that will remove the debris but will not damage the probe elements. Generally, the “positive” microfeatures can have several types of geometries including pyramids 401, round or square columns 404 with uniform plateau, or various curved shapes 403 with smaller than 40 um square or round plateaus, etc. The microfeature type and “positive” geometry may be adjusted during the manufacturing of a cleaning layer such that the material can be used reshape, sharpen or refurbish, the probe element tips and the probe element structure.

The dimensions of the “positive” features may have a base-to-top of each microfeature above the base reference plane 408 of 25 um to 500 um, a top surface area geometry which can be flat or shaped and that has dimensions ranging in XY dimensions from 20 um up to the XY dimensions of the microfeature base, sides of the positive feature can be straight or curved, and plateau-to-plateau spacing (the distance between each microfeature) of 50 um to 250 um.

In another embodiment of the cleaning medium 221 (shown in FIG. 7), the maximum cleaning efficiency of the cleaning material can be improved using a plurality of “negative” uniformly shaped and regularly spaced, geometric microfeatures, such as a plurality of inverted micro-pyramids 601, a plurality of micro-columns 603, or a plurality of curved inverted micro-pyramids 605, of a pre-determined geometry as shown in FIGS. 6A-6C. In other embodiments, the microfeatures may be variably spaced across the cleaning medium 221. In FIG. 7, the cleaning media 221 is constructed from a single layer of cleaning pad with “negative” microfeatures 251 onto a combination of intermediate compliant or rigid layers 207 with pre-determined predetermined properties.

As an example of one type of functional “negative” microfeature construction, the microfeatures shown in FIGS. 6A, 6B, 6C can be created using a combination of precision fabrication methods such as casting or molding whereby the cleaning pad is built such that the plateau has a dimension of less than 40 um, a height of less than 100 um, and a bottom-to-bottom spacing of less than 250 um. In these examples, each microfeature is recessed into a base reference plane 608. In the example microfeature 601 shown in FIG. 6A, each pyramid microfeature 602 has a 25 um square bottom, with a 40 um height, at a bottom-to-bottom spacing of 100 um. For this construction, the 3D features are attained through a precision fabrication process such that the cleaning pad and microfeatures have a uniform composition. The size and geometry of the “negative” microfeatures may vary according the configuration and material of the contact elements to achieve a pad that will remove the debris but will not damage the probe elements. Generally, the “negative” microfeatures can have several types of geometries including inverted pyramids 602, round or square columns 604 with uniform bottom, or various curved inverted shapes 406 with smaller than 40 um square or round bases, etc. The microfeature type and “negative” geometry may be adjusted during the manufacturing of a cleaning layer such that the material can be used reshape, sharpen or refurbish, the probe element tips and the probe element structure. As an example, the negative microfeatures like those shown in FIG. 6A or FIG. 6C may be used to clean advanced microcantilever contact elements since the physical shape and dimension of those negative microfeatures clean all of the critical surfaces of the microcantilever contact elements.

The dimensions of the “negative” features may have a base-to-top of each microfeature below the base reference plane 608 of 25 um to 500 um, a bottom surface area geometry which can be flat or shaped and that has dimensions ranging in XY dimensions from 20 um up to the XY dimensions of the microfeature opening, sides of the negative feature can be straight or curved, and bottom-to-bottom spacing (the distance between each microfeature) of 50 um to 250 um.

Another embodiment of the cleaning pad/media/device with the functionalized microfeatures is shown in FIGS. 8A-8C that show examples of enlarged sectional views of a cleaning material 800 with “positive” microfeatures layer (with micro-pyramids 802, micro-columns 804, curved micro-pyramids 806) underneath a layer of polymer 10 to 100 um thick with predetermined properties that has been applied across the surface of the “positive” features (801, 803, and 805, respectively). The polymer layer is applied across the top surface and within the spacing between the microfeatures to a predetermined thickness of less than 100 um. The polymer can be tacky and without abrasives or loaded with an abrasive. Typical abrasives that may be incorporated into the polymer may include aluminum oxide, silicon carbide, and diamond although the abrasive particles may also be other well-known abrasive materials with Mohs Hardness of 7 or greater. The amount and size of the abrasive material may vary according the configuration of the microfeatures of the cleaning pad or based on the material and geometry of the contact elements in order to achieve a pad that will remove and collect the debris but will not damage the contact elements or support hardware.

FIGS. 8D-8F that show examples of enlarged sectional views of a cleaning material 800 with “positive” microfeatures layer (with micro-pyramids 802, micro-columns 804, curved micro-pyramids 806) underneath a layer of polymer 10 to 100 um thick with predetermined properties that has been applied across the surface of the “positive” features (801, 803, and 805, respectively). The microfeatured cleaning pad layer can then be constructed onto a one or more intermediate complaint or rigid material layers below a cleaning pad layer of predetermined properties and a protective liner.

Another embodiment of the cleaning pad/media/device with the functionalized microfeatures is shown in FIGS. 9A-9C that show examples of enlarged sectional views of a cleaning materials with “negative” microfeatures (inverted micro-pyramids 901, inverted micro-columns 903, curved inverted micro-pyramids 905 with a layer of polymer 10 to 100 um thick with predetermined properties is applied across the surface of the “negative” features (901, 903, and 905, respectively). The polymer layer is applied across the top surface and into the depressions (cavities) of the “negative” microfeatures thus coating an interior surface of each negative microfeature. The polymer can be tacky and without abrasives or loaded with abrasive particles. Typical abrasives that may be incorporated into the polymer may include aluminum oxide, silicon carbide, and diamond although the abrasive particles may also be other well-known abrasive materials with Mohs Hardness of 7 or greater. The amount and size of the abrasive material may vary according the configuration of the microfeatures of the cleaning pad or based on the material and geometry of the contact elements in order to achieve a pad that will remove and collect the debris but will not damage the contact elements or support hardware. The microfeatured cleaning pad layer can then be constructed onto a one or more intermediate complaint or rigid material layers below a cleaning pad layer of predetermined properties and a protective liner. The above embodiments would be typically used for a system that tests the wafers or one or more dies on a semiconductor wafer prior to being singulated and/or encapsulated into an assembled package.

Now, another embodiment of the cleaning device will be described wherein the cleaning device may be used for cleaning contact elements that are used to electrically test the DUTs wherein an individual semiconductor device from the wafer has been encapsulated into a material 501, such as plastic, as shown in FIG. 10A. In this illustrative example, the cleaning device may also be used with an ATE and tester for handling and testing packaged integrated circuits (IC). The IC package may have one or more electrical leads or solder balls extending out from the package that conduct electrical signals (FIG. 1B), including power signal, ground and I/O signal, etc., with the die or dice inside of the package 15. The tester interface, in this case called test socket 12, will have a plurality of contact elements 13 (similar to the probe card tester described above) that contact the leads of the package and test the electrical characteristics of the packaged DUT. Commonly, the contact elements are mounted onto various spring-loaded probes or flexible contact elements and can have a geometrical configuration with single spear-like, crown-like, or other multi-tine contactors.

The flexible contact elements can be held within an elastomer, silicone-rubber layer held within a memory socket, logic socket, burn in socket, or interposer.

Similar to the probe card cleaner embodiment, the cleaning device for the encapsulated device may approximate a DUT shape with a substrate onto which the cleaning pad material 503 has been applied as shown in FIG. 10B such that contact elements of the test socket may contact the cleaning pad surface periodically to remove debris from the tips of the probe elements. The size of the cleaning device may be modified to fit the size and shape of the particular socket or to approximate the dimensions of a particular device. In the microfeatured embodiment shown in FIG. 10B, the cleaning material 503 is configured to simulate the size, geometry, spacing, and exact layout of the solder balls from the DUT.

In FIG. 11A, a cleaning device 600 may have the layers described above and a cleaning pad layer 601 that has a plurality of cleaning balls 603 made of cleaning material that match the DUT solder ball geometry will have an abrasiveness such that the reciprocal pressure on the contact elements imparts efficient cleaning to remove and collect debris from the contact elements. The height, diameter, and location of the cleaning-balls is predetermined according to the configuration of the DUT and material of the contact elements. The spacing, geometry, and abrasiveness of the cleaning-balls is such that the reciprocal pressure on the contact elements imparts efficient cleaning to remove and collect debris from the contact elements.

In another embodiment, FIG. 11B shows a sectional view of the cleaning device 600 with the cleaning pad layer 602 with a plurality of cleaning-balls 603 that match the DUT solder ball geometry as described above which further has a uniform layer of cleaning polymer 10 to 100 um thick 605 with predetermined properties applied across the surface. Thus, the number of pad/polymer/substrate layers and functionalized microfeatures of the cleaning surface are controlled to provide control of the overall thickness of the cleaning device as well as the compliance of the thickness of the cleaning. This multi-layer embodiment with the cleaning-balls would also provide cleaning accurate within the guide-holes of a floating-floor socket as well as the interior of the socket and contactors of the prober.

Now, a method for cleaning a plurality of probe elements and supporting hardware or solder balls using the disclosed cleaning devices with functionalized microfeatures will be described with reference to FIG. 12. The insertion of the contact elements of the tester interface or solder balls for an encapsulated integrated circuit into a cleaning device removes adherent debris from the contact element and supporting hardware or DUT without leaving any organic residue that must be subsequently removed with an additional on-line of off-line process. Furthermore, the over-all electrical characteristics of the contact element and the geometry are unaffected; however, the overall electrical performance needed for high yield and low contact resistance is recovered. The method accomplishes the goal of removing the debris from contact elements without removing the tester interface from the ATE, thereby increasing the productivity of the tester. The cleaning device, that may have the same size and shape as typical DUTs being tested by the tester and may be inserted into a predetermined cleaning tray. Alternatively, the cleaning material with the functionalized microfeatures may be placed into a substrate, such as a wafer, that may be placed into the wafer carriers and thus perform the cleaning. The cleaning material layer of the device has predetermined physical, mechanical, and geometrical properties according the configuration and material of the contact elements and supporting hardware of the tester interface.

As described above, this cleaning step may occur either when the cleaning device is periodically installed from the cleaning tray positioned under the contact elements of tester interface or every time from the wafer cassette, or anytime the ATE executes a cleaning operation of the contact elements with the cleaning material installed onto the burnishing plate. Use of the cleaning device does not interrupt, in any way, the operation of the ATE since the cleaning of the contact elements is accomplished during the normal operation of the testing machine. In this manner, the cleaning device is inexpensive and permits the contact element to be cleaned and/or shaped without removing the contact elements or tester interface from the ATE.

The methods and apparatus provide one or more advantages including but not limited to maintaining clean contactors and contact pins. While the disclosure has been described with reference to certain illustrative embodiments, those described herein are not intended to be construed in a limiting sense. For example, variations or combinations of steps in the embodiments shown and described may be used in particular cases without departure from the disclosure. Various modifications and combinations of the illustrative embodiments as well as other advantages and embodiments of the disclosure will be apparent to persons skilled in the arts upon reference to the drawings, description, and claims. It is intended that the scope of the disclosure be defined by the claims appended hereto and their equivalents. While the foregoing has been with reference to a particular embodiment of the invention, it will be appreciated by those skilled in the art that changes in this embodiment may be made without departing from the principles and spirit of the disclosure, the scope of which is defined by the appended claims.

FIG. 12 is a flowchart showing a method 1200 for cleaning semiconductor devices or testers or probe elements using the various embodiments of the disclosed cleaning material with the functionalized microfeatures. The method in FIG. 12 is for cleaning a tester interface, but it is understood that a similar method would be used to clean a DUT, etc. In the method, the tester performs its tests 1202. The tester (that has a control system) or a separate computer system may determine if it is time to clean the tester 1204 based on a time interval or the measurement of the characteristics of the testing process. If cleaning is not needed, then the tester continues testing 1202. If it is determined to be time to clean the tester, a cleaning device having the functionalized microfeatures may be moved into a cleaning position (1206) by various means and the cleaning is performed using the cleaning material (1208) without taking the tester off-line and thus during the normal testing procedure of the testing machine. Once the cleaning is completed, the tester resumes its testing function (1210).

TEST RESULTS

FIGS. 13A and 13B illustrate probe tip cleaning using a typical cleaning material. Specifically, FIG. 13A shows that a typical cleaning material without the functionalized microfeatures makes contact with the probe tips so that no all of the critical surfaces of the probe are effectively cleaned. An example of the probes after the cleaning with the typical cleaning material is shown in FIG. 13B in which various debris is still attached to or adhered to the probe which results in the issues described above.

In contrast, FIGS. 14A and 14B illustrate the same probe tips as FIG. 13B being cleaned using the functionalized microfeatures cleaning material. As shown in FIG. 14A, each probe (including the sloping slides and the tip, collectively the entire probe area) are contact by the sides of the functionalized microfeatures. An example of the probes after the cleaning with the cleaning material having the functionalized microfeatures is shown in FIG. 14B in which each probe is much cleaner since all of the critical surfaces of each probe is cleaned.

The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical applications, to thereby enable others skilled in the art to best utilize the disclosure and various embodiments with various modifications as are suited to the particular use contemplated.

The system and method disclosed herein may be implemented via one or more components, systems, servers, appliances, other subcomponents, or distributed between such elements. When implemented as a system, such systems may include an/or involve, inter alia, components such as software modules, general-purpose CPU, RAM, etc. found in general-purpose computers. In implementations where the innovations reside on a server, such a server may include or involve components such as CPU, RAM, etc., such as those found in general-purpose computers.

Additionally, the system and method herein may be achieved via implementations with disparate or entirely different software, hardware and/or firmware components, beyond that set forth above. With regard to such other components (e.g., software, processing components, etc.) and/or computer-readable media associated with or embodying the present inventions, for example, aspects of the innovations herein may be implemented consistent with numerous general purpose or special purpose computing systems or configurations. Various exemplary computing systems, environments, and/or configurations that may be suitable for use with the innovations herein may include, but are not limited to: software or other components within or embodied on personal computers, servers or server computing devices such as routing/connectivity components, hand-held or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, consumer electronic devices, network PCs, other existing computer platforms, distributed computing environments that include one or more of the above systems or devices, etc.

In some instances, aspects of the system and method may be achieved via or performed by logic and/or logic instructions including program modules, executed in association with such components or circuitry, for example. In general, program modules may include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular instructions herein. The inventions may also be practiced in the context of distributed software, computer, or circuit settings where circuitry is connected via communication buses, circuitry or links. In distributed settings, control/instructions may occur from both local and remote computer storage media including memory storage devices.

The software, circuitry and components herein may also include and/or utilize one or more type of computer readable media. Computer readable media can be any available media that is resident on, associable with, or can be accessed by such circuits and/or computing components. By way of example, and not limitation, computer readable media may comprise computer storage media and communication media. Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and can accessed by computing component. Communication media may comprise computer readable instructions, data structures, program modules and/or other components. Further, communication media may include wired media such as a wired network or direct-wired connection, however no media of any such type herein includes transitory media. Combinations of the any of the above are also included within the scope of computer readable media.

In the present description, the terms component, module, device, etc. may refer to any type of logical or functional software elements, circuits, blocks and/or processes that may be implemented in a variety of ways. For example, the functions of various circuits and/or blocks can be combined with one another into any other number of modules. Each module may even be implemented as a software program stored on a tangible memory (e.g., random access memory, read only memory, CD-ROM memory, hard disk drive, etc.) to be read by a central processing unit to implement the functions of the innovations herein. Or, the modules can comprise programming instructions transmitted to a general purpose computer or to processing/graphics hardware via a transmission carrier wave. Also, the modules can be implemented as hardware logic circuitry implementing the functions encompassed by the innovations herein. Finally, the modules can be implemented using special purpose instructions (SIMD instructions), field programmable logic arrays or any mix thereof which provides the desired level performance and cost.

As disclosed herein, features consistent with the disclosure may be implemented via computer-hardware, software and/or firmware. For example, the systems and methods disclosed herein may be embodied in various forms including, for example, a data processor, such as a computer that also includes a database, digital electronic circuitry, firmware, software, or in combinations of them. Further, while some of the disclosed implementations describe specific hardware components, systems and methods consistent with the innovations herein may be implemented with any combination of hardware, software and/or firmware. Moreover, the above-noted features and other aspects and principles of the innovations herein may be implemented in various environments. Such environments and related applications may be specially constructed for performing the various routines, processes and/or operations according to the invention or they may include a general-purpose computer or computing platform selectively activated or reconfigured by code to provide the necessary functionality. The processes disclosed herein are not inherently related to any particular computer, network, architecture, environment, or other apparatus, and may be implemented by a suitable combination of hardware, software, and/or firmware. For example, various general-purpose machines may be used with programs written in accordance with teachings of the invention, or it may be more convenient to construct a specialized apparatus or system to perform the required methods and techniques.

Aspects of the method and system described herein, such as the logic, may also be implemented as functionality programmed into any of a variety of circuitry, including programmable logic devices (“PLDs”), such as field programmable gate arrays (“FPGAs”), programmable array logic (“PAL”) devices, electrically programmable logic and memory devices and standard cell-based devices, as well as application specific integrated circuits. Some other possibilities for implementing aspects include: memory devices, microcontrollers with memory (such as EEPROM), embedded microprocessors, firmware, software, etc. Furthermore, aspects may be embodied in microprocessors having software-based circuit emulation, discrete logic (sequential and combinatorial), custom devices, fuzzy (neural) logic, quantum devices, and hybrids of any of the above device types. The underlying device technologies may be provided in a variety of component types, e.g., metal-oxide semiconductor field-effect transistor (“MOSFET”) technologies like complementary metal-oxide semiconductor (“CMOS”), bipolar technologies like emitter-coupled logic (“ECL”), polymer technologies (e.g., silicon-conjugated polymer and metal-conjugated polymer-metal structures), mixed analog and digital, and so on.

It should also be noted that the various logic and/or functions disclosed herein may be enabled using any number of combinations of hardware, firmware, and/or as data and/or instructions embodied in various machine-readable or computer-readable media, in terms of their behavioral, register transfer, logic component, and/or other characteristics. Computer-readable media in which such formatted data and/or instructions may be embodied include, but are not limited to, non-volatile storage media in various forms (e.g., optical, magnetic or semiconductor storage media) though again does not include transitory media. Unless the context clearly requires otherwise, throughout the description, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in a sense of “including, but not limited to.” Words using the singular or plural number also include the plural or singular number respectively. Additionally, the words “herein,” “hereunder,” “above,” “below,” and words of similar import refer to this application as a whole and not to any particular portions of this application. When the word “or” is used in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list and any combination of the items in the list.

Although certain presently preferred implementations of the invention have been specifically described herein, it will be apparent to those skilled in the art to which the invention pertains that variations and modifications of the various implementations shown and described herein may be made without departing from the spirit and scope of the invention. Accordingly, it is intended that the invention be limited only to the extent required by the applicable rules of law.

While the foregoing has been with reference to a particular embodiment of the disclosure, it will be appreciated by those skilled in the art that changes in this embodiment may be made without departing from the principles and spirit of the disclosure, the scope of which is defined by the appended claims. 

What is claimed is:
 1. A method for cleaning contact elements and support structures of a testing interface used for wafer level or package level IC semiconductor device testing, the method comprising: performing a testing operation of the wafer level or package level IC semiconductor devices; and performing a cleaning operation using a cleaning device that has a cleaning media having a plurality of functionalized microfeatures that each have a body with a width a height, a spacing between each body and dimensional properties that optimize the cleaning media so that the contact area and surrounding support hardware are cleaned without modification or damage, each microfeature extending away from a top surface of the cleaning media and the cleaning media having a plurality of abrasive particles having a Mohs Hardness of 7 or greater uniformly distributed within the body of each microfeature, a cleaning layer applied across the top surface of the cleaning media having predetermined characteristics that clean contaminants from the pin contact elements and support hardware and one or more intermediate rigid or compliant underlayers underneath the cleaning media, wherein each underlayer has a modulus of elasticity range between more than 40-MPa to 600-MPa, each layer has a thickness between 25-um and 300-um and each layer has a hardness between 30 Shore A and 90 Shore A.
 2. The method of claim 1, wherein performing a cleaning operation using a cleaning device further comprises using a polymer layer that is 10 to 100 um thick that has a predetermined specific gravity, elasticity, tackiness, planarity, thickness and porosity.
 3. The method of claim 1, wherein performing a cleaning operation using a cleaning device further comprises using a plurality of positive microfeatures that extends upwards away from the top surface of the cleaning media.
 4. The method of claim 1, wherein performing a cleaning operation using a cleaning device further comprises using a plurality of negative microfeature that extends downwards away from the top surface of the cleaning media.
 5. A method for cleaning pin contact elements and support hardware in a semiconductor testing apparatus, the method comprising: performing testing of a device under test having a predetermined configuration of one of solder balls, pillars, copper-pillar bumps, and gold bumps; and performing cleaning of the pin contact elements and support hardware using a cleaning device having a cleaning media with a plurality of geometrical surface features that emulate wherein the cleaning balls and cleaning pillars are further comprised of a plurality of abrasive particles distributed within the features and having a Mohs Hardness of 7 or greater for cleaning contact elements and support structures of testing interfaces, a cleaning layer applied across a top surface of each geometric surface feature and along a side of each geometric surface feature having predetermined characteristics that clean contaminants from the pin contact elements and support hardware and a substrate onto which the cleaning media is attached, having a configuration suitable to be introduced into the testing apparatus during normal testing operating of the testing apparatus, wherein the substrate comprises a surrogate semiconductor wafer or packaged IC device. 